1. Field of the Invention
The present invention relates to disk drives for computer systems. More particularly, the present invention relates to a disk drive implementing shared buffer memory with reduced interrupt latency.
2. Description of the Prior Art
FIG. 1 shows an example configuration of a prior art disk drive wherein one or more disks 2 and heads 3 are housed in a head disk assembly (HDA) 4. The HDA 4 also houses a voice coil motor (VCM) 6 for rotating one or more actuator arms about a pivot in order to actuate the heads 3 over the respective disk surfaces. A printed circuit board (PCB) is mounted to the HDA 4, wherein one or more integrated circuits for controlling operation of the disk drive are mounted on the PCB, including a microprocessor (uP) 8 for executing code segments of a control routine. The microprocessor 8 typically accesses a fast uP cache 10 (e.g., an SRAM) through a uP cache controller 11 which caches control routine op codes being executed as well as control routine data.
The code segments of the control routine are typically stored on the disk 2 and loaded into an external buffer memory 12 (e.g., an SDRAM) when the disk drive is powered on. As the microprocessor 8 executes the control routine, the uP cache controller 11 transfers a burst of corresponding control routine op codes from the external buffer memory 12 into the uP cache 10 for fast access by the microprocessor 8. Since the buffer memory 12 is typically shared with other control components, a buffer controller 14 implements an arbitration algorithm to arbitrate access to the buffer memory 12. Example control components that may share access to the buffer memory 12 include a host interface 16, a disk interface 18, a data cache controller 20, and an ECC controller 22, one or more of which may be integrated with the microprocessor 8 in a system on a chip (SOC), or implemented as separate integrated circuits.
The host interface 16 facilitates data transfer between the disk drive and a host 24 during read and write operations. That is, during read operations data read from the disk 2 is staged in the buffer memory 12 before the host interface 16 transmits the read data to the host 24, and during write operations data received from the host 24 is staged in the buffer memory 12 before being written to the disk 2. The disk interface 18 performs the actual interface functions with the HDA 4 in order to write data stored in the buffer 12 to the disk 2, and store data into the buffer 12 that is read from the disk 2. The data cache controller 20 accesses a data cache area of the buffer memory 12 in order to implement a suitable user data caching algorithm, and the ECC controller 22 implements a suitable error correction algorithm on data read from the disk 4 and stored in the buffer 12.
The buffer controller 14 assigns a priority level to each control component attempting to access the buffer memory 12 so that the more time critical components are granted accesses soonest. For example, the disk interface 18 may be given the highest priority in the arbitration scheme so that disk accesses are serviced in synchronism with the disk 2 rotating. Otherwise there would be an undesirable latency due to slipped revolutions when reading or writing data blocks to the disk. Similarly, the host interface 16 may be given a high priority in order to minimize any perceived access latency by the end user. This means the uP cache controller 11 is given a priority level lower than a number of other control components, and therefore the microprocessor 8 may encounter a long arbitration delay if components of higher priority are attempting a concurrent access to the buffer memory 12.
The microprocessor 8 is held in a wait state while the uP cache controller 11 is waiting to access the buffer memory 12, which prevents the microprocessor 8 from servicing what may be time critical interrupts 26. For example, a servo controller 28 may generate an interrupt at each servo wedge, signaling the microprocessor 8 that it is time to compute an updated VCM 6 control command for positioning the head 3, or a spindle motor command for controlling the rotational speed of the disk 2. Any delay before the microprocessor 8 services these interrupts reduces the performance of the closed-loop servo systems.
There is, therefore, a need to reduce the interrupt latency in a disk drive that employs a shared buffer memory.